Cisco UCS-CPU-E52609BC= Datasheet download pdf (Page 37)

Cisco UCS B200 M3 Blade Server

SUPPLEMENTAL MATERIAL

CPUs and DIMMs

Physical Layout

Memory is organized as shown in Figure 6.

Figure 6 UCS B200 M3 Memory Organization

Each CPU controls four memory channels, as follows:

■ CPU1: Channels A, B, C, and D

— Bank 0 - A0, B0, C0, and D0 (blue DIMM slots)

— Bank 1 - A1, B1, C1, and D1 (black DIMM slots)

— Bank 2 - A2, B2, C2, and D2 (white DIMM slots)

■ CPU2: Channels E, F, G, and H

— Bank 0 - E0, F0, G0, and H0 (blue DIMM slots)

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 57 58

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Cisco UCS-CPU-E52609BC= Datasheet Page 37