Cisco MGX 8230 Specifications download pdf (Page 206)

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Cisco MGX 8230 Edge Concentrator Installation and Configuration

Release 1.1.31, Part Number 78-11215-03 Rev. B0, May 2001

Chapter 6 Card and Service Configuration

Circuit Emulation Service Module for T3 and E3

The main function of the Circuit Emulation Service Module (CESM) is to provide a constant bit rate

(CBR) service. The CESM converts data streams into CBR AAL1 cells according to the CES-IS

specifications of the ATM Forum for unstructured transport across an ATM network. Unstructured

transport means the CESM does not interpret or modify framing bits, so a high-speed CESM creates a

single data pipe The most common application is legacy support for digitized voice from a PBX or video

from a codec. Using circuit emulation, a company can expand its data communication network without

specific voice or video cards to meet its voice or teleconferencing requirements.

The higher speed CESM uses a T3 or E3 line. The card set consists of an MGX-CESM-T3 or

MGX-CESM-E3 front card and either a BNC-2T3 or BNC-2E3 back card. In this CESM application,

only one line on the two-port back card is operational. Furthermore, it supports one logical port and one

logical connection (as a data pipe) on the line and runs at the full T3 or E3 rate. Although the typical

connection setup is the three-segment connection across an ATM network, the CESM can support a DAX

connection. Up to 26 CESM card sets can operate in an MGX 8230 shelf.

Features

The MGX-CESM-T3 or MGX-CESM-E3 provide the following:

• Unstructured data transfer at 44.736 Mbps (1189980 cells per second) for T3 or 34.368 Mbps (91405

cells per second) for E3

• Synchronous timing by either a local clock sourced on the PXM1 or loop timing (transmit clock

derived from receive clock on the line)

• 1:1 redundancy is through a Y-cable

• Programmable egress buffer size (in the form of cell delay variation)

• Programmable cell delay variation tolerance (CDVT)

• Per VC queuing for the transmit and receive directions

• An idle code suppression option

• Bit count integrity when a lost AAL1 cell condition arises

• Alarm state definitions per G.704

• Trunk conditioning by way of framed AIS for T3 and unframed, alternating 1s and 0s for E3

• On-board bit error rate testing (BERT)

Cell Delay Treatment

You can configure a tolerable variation in the cell arrival time (CDVT) for the receive buffer. After an

underrun, the receiver places the contents of the first cell to arrive in a receive buffer then plays it out at

least one CDVT value later. The maximum cell delay and CDVT (or jitter) are:

• For T3

–

Cell delay of 4 msec

–

CDVT of 1.5 msec in increments of 125 microseconds

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Cisco MGX 8230 Specifications Page 206