Cisco MGX 8950 Specifications download pdf (Page 68)

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Cisco MGX 8850 (PXM1E/PXM45), Cisco MGX 8950, Cisco MGX 8830, and Cisco MGX 8880 Configuration Guide

Release 5.0.10, OL-3845-01 Rev. B0, August 16, 2004

Chapter 1 Preparing for Configuration

Guidelines for Creating a Network Clock Source Plan

Figure 1-6 Example Network Clock Source Topology with a Single Master Clock Source

In Figure 1-6, Switch 1 provides the master network clock source to the rest of the network and uses

highly accurate external Building Integrated Timing System (BITS) clock sources to time its

transmissions. These BITS clock sources are T1 or E1 lines with Stratum-1, 2, or 3 clock signals.

Switch 1 uses one BITS line as the primary clock source and uses the secondary BITS source only if a

failure occurs on the primary BITS line. If both BITS sources fail, the internal Stratum-3 clock takes

over.

Note The PXM45 and PXM1E cards support T1 data (1.544Mbps) and E1 data (2.048Mbps) clock sources;

they do not support T1 or E1 sync clock sources. The PXM1 supports both T1 and E1 data types and an

E1 sync (2.048MHz) line as a clock input.

Switches 2 through 5 synchronize to Switch 1 with the master clock signal, which they receive over NNI

trunks. Switch 6 synchronizes its communications using the master clock source, which is forwarded

from Switch 3. In this topology, all switches synchronize to the same clock source, and this configuration

reduces the possibility that two switches might not be able to synchronize communications.

80146

Switch 2 Switch 3

Switch 4 Switch 5

Switch 1 –

master clock

source

NNI

trunks with

clocks

NNI

trunks with

clocks

P = Primary clock source

S = Secondary clock source

Switch 6

BITS

clock

sources

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